Computer memories may be conveniently classified in terms of whether or not the memory retains the information stored therein when power is removed from the memory. Conventional DRAMs and SRAMs are examples of memories that lose their contents when power is removed. EEPROM and flash RAM are examples of non-volatile memories. The cost of non-volatile memories per bit remains sufficiently high to discourage their use in many applications. In addition, the underlying memory structures may only be written a relatively small number of times compared to volatile memories. For example, an EEPROM memory cell can only be written approximately 10.sup.4 times. In addition, the time required to write data into an EEPROM is much longer than that required to write volatile memories. Hence, EEPROM cells have a relatively limited class of applications.
One class of non-volatile memory device stores information by altering the direction of polarization of a ferroelectric dielectric layer within the device. These devices are structurally similar to capacitors in which the dielectric layer is replaced by a ferroelectric material. In these devices, the ferroelectric dielectric may be polarized in one of two directions. The direction of polarization is used to store information, a "1" corresponding to one direction of polarization and a "0" corresponding to the other direction of polarization. The polarization of the dielectric is maintained when power is removed from the system, thus providing non-volatile operation.
The direction of the polarization may be sensed by applying a potential sufficient to switch the polarization across the capacitor. For the purposes of this discussion, assume that the applied potential difference is such that it would switch the dielectric to the polarization state corresponding to a "1". If the capacitor was polarized such that it stored a "1" prior to the application of the read potential, the polarization will not be altered by the read voltage. However, if the capacitor was polarized such that it stored a "0" prior to the application of the read potential, the polarization direction will switch. This switching will give rise to a current that flows from one plate of the capacitor to the other. A sense amplifier measures the current that flows in response to the read potential to determine the state of the capacitor. Once the capacitor has been read, the data must be rewritten in the capacitor if the read potential caused the state of the capacitor to switch.
To construct a memory based on such capacitors, each capacitor is connected to a pass transistor that isolates, or connects, the capacitor to a bit line via one plate of the capacitor. The other plate of the capacitor will be referred to as the "common plate" in the following discussion. In general, the one-bit memory cells consisting of a capacitor and its associated pass transistor are organized into words. All of the bits in a given word are typically read at the same time. For example, in one memory design, the pass gates for each pass transistor in the word are connected to a common word line and the common plates are connected to a "plate line" associated with the word. Various control signals are applied to the word and plate lines during the reading and writing of the memory.
In general, a ferroelectric memory is constructed by first fabricating the pass transistors and associated circuitry utilizing conventional CMOS fabrication processes. The surface of the wafer is then covered with a protective layer and the capacitor structures fabricated on top of the protective layer. The bottom plate of each capacitor is constructed over the source of its corresponding pass transistor. A stack consisting of the ferroelectric material and the top plate of the capacitor is then constructed over the bottom electrode. A protective layer is then deposited over the capacitors and metal run on top of the protective layer to provide the plate lines. The top plates are connected to the plate lines through vias in the protective layer.
The additional masks and deposition steps needed to construct the capacitors and make the connections to the plate lines increase the cost and lower the yield of devices. In addition, the area occupied by the plate lines increases the device area as compared to non-ferroelectric memories.
Broadly, it is the object of the present invention to provide an improved ferroelectric memory.
It is a further object of the present invention to provide a ferroelectric memory requiring fewer masks than prior art devices.
It is a still further object of the present invention to provide a ferroelectric memory that does not require separate plate lines.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.